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标题:Oversampling ∑Δ Analog-to-Digital Converters Modeling Based on VHDL
时间:2019-11-19 21:48:06
DOI:10.1023/A:1008211605358
作者:Robert Baraniecki;Przemysław Dabrowski;Konrad Hejn
关键词:RTL synthesis;Sigma-delta modulator;VHDL;behavioral modeling and simulation;decimator
出版源: Analog Integrated Circuits and Signal Processing ,1998 ,16 (2) :101-109
摘要:The paper presents a VHDL model of an oversampling ∑Δ analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes, only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital part is described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.
大小:339 kb
页数:10 PAGES
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